The present invention relates generally to logic circuits and, more particularly, to full-rail differential logic circuits.
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG. 3(c), in xe2x80x9cHIGH SPEED CMOS DESIGN STYLESxe2x80x9d by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1 shows a prior art full-rail differential logic circuit 100 similar to that discussed in the Bernstein et al. reference. As seen in FIG. 1, prior art full-rail differential logic circuit 100 included six transistors: PFET 105, PFET 107, NFET 109, PFET 115, PFET 117 and NFET 121. Prior art full-rail differential logic circuit 100 also included: differential logic 123 with inputs 151 and 153; out terminal 111; and outBar terminal 113. Prior art full-rail differential logic circuit 100 is activated from a delayed clock signal CLKA. As shown in FIG. 1, signal CLKA was supplied to: gate 116 of PFET 115; gate 118 of PFET 117; gate 129 of NFET 109; and gate 122 of NFET 121.
Prior art full-rail differential logic circuit 100 worked reasonably well under conditions of a light load, for instance under conditions where fan out is less than four. However, prior art full-rail differential logic circuit 100 was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of prior art full-rail differential logic circuit 100 arose primarily because under heavy load conditions logic network 123 had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic network 123 was large, slow and inefficient. The problem was further aggravated as additional prior art full-rail differential logic circuits 100 were cascaded together to form the chains commonly used in the industry. Consequently, the full potential of prior art full-rail differential logic circuits 100 was not realized and their use was narrowly limited to light load applications.
What is needed is a method and apparatus for creating full-rail differential logic circuits that are capable of efficient use under heavy loads and are therefore more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits.
The modified full-rail differential logic circuits of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the modified full-rail differential logic circuits of the invention is additionally delayed with respect to the delayed clock that drives the full-rail differential logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic network to provide the driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits. In addition, the modified full-rail differential logic circuits of the invention require less space, are simpler, dissipate less heat and have fewer components to potentially fail.
The modified full-rail differential logic circuits of the invention can be cascaded together to form the chains commonly used in the industry. When the modified full-rail differential logic circuits of the invention are cascaded together, the advantages of the modified full-rail differential logic circuits of the invention are particularly evident and the gains in terms of efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of modified full-rail differential logic circuits. The chain includes a first modified full-rail differential logic circuit. The first modified full-rail differential logic circuit includes: a first modified full-rail differential logic circuit first clock input terminal; at least one first modified full-rail differential logic circuit data input terminal; at least one first modified full-rail differential logic circuit data output terminal; and a first modified full-rail differential logic circuit second clock input terminal.
The cascaded chain of the invention also includes a second modified full-rail differential logic circuit. The second modified full-rail differential logic circuit includes: a second modified full-rail differential logic circuit first clock input terminal; at least one second modified full-rail differential logic circuit data input terminal; at least one second modified full-rail differential logic circuit data output terminal; and a second modified full-rail differential logic circuit second clock input terminal.
According to the invention, the at least one first modified full-rail differential logic circuit data output terminal is coupled to the at least one second modified full-rail differential logic circuit data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first modified full-rail differential logic circuit first clock input terminal and a second clock signal is coupled to the first modified full-rail differential logic circuit second clock input terminal and the second modified full-rail differential logic circuit first clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first modified full-rail differential logic circuit clock input terminal and the second modified full-rail differential logic circuit first clock input terminal to provide the predetermined delay time. In one embodiment of the invention, the delay circuit is also coupled between the first modified full-rail differential logic circuit clock input terminal and the first modified full-rail differential logic circuit second clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a modified full-rail differential logic circuit that includes a modified full-rail differential logic circuit out terminal and a modified full-rail differential logic circuit outBar terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the modified full-rail differential logic circuit out terminal. The first transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first node is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the modified full-rail differential logic circuit outBar terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor control electrode is coupled to the third transistor first flow electrode and the modified full-rail differential logic circuit outBar terminal. The second transistor control electrode is coupled to the third transistor second flow electrode and the modified full-rail differential logic circuit out terminal. The third transistor control electrode is coupled to a clock signal CLKA.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The first node is coupled to the fourth transistor first flow electrode and the fourth transistor second flow electrode is coupled to the modified full-rail differential logic circuit out terminal. The fourth transistor control electrode is coupled to the clock signal CLKA. The fourth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The first node is coupled to the fifth transistor first flow electrode and the fifth transistor second flow electrode is coupled to the modified full-rail differential logic circuit outBar terminal. The fifth transistor control electrode is coupled to the clock signal CLKA. The fifth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a sense amplifier circuit coupled between the modified full-rail differential logic circuit out terminal and the modified full-rail differential logic circuit outBar terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit sense amplifier circuit includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The first transistor second flow electrode is coupled to the sixth transistor first flow electrode. The sixth transistor second flow electrode is coupled to a second node. The sixth transistor control electrode is coupled to the third transistor first flow electrode and the modified full-rail differential logic circuit outbar terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit sense amplifier circuit also includes a seventh transistor, the seventh transistor including a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode. The second transistor second flow electrode is coupled to the seventh transistor first flow electrode. The seventh transistor second flow electrode is coupled to the second node. The seventh transistor control electrode is coupled to the third transistor second flow electrode and the modified full-rail differential logic circuit out terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit sense amplifier circuit also includes an eighth transistor, the eighth transistor including an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode. The eighth transistor first flow electrode is coupled to the second node and the eighth transistor second flow electrode is coupled to a second supply voltage. A clock signal CLKB is coupled to the eighth transistor control electrode of the modified full-rail differential logic circuit sense amplifier circuit. In one embodiment of the invention, the clock signal CLKB is delayed a predetermined time with respect to the clock signal CLKA.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a logic block, the logic block including at least one logic block input terminal, a logic block out terminal and a logic block outbar terminal. The logic block out terminal is coupled to the modified full-rail differential logic circuit out terminal and the logic block outBar terminal is coupled to the modified full-rail differential logic circuit outBar terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a ninth transistor, the ninth transistor including a ninth transistor first flow electrode, a ninth transistor second flow electrode and a ninth transistor control electrode. The ninth transistor first flow electrode is coupled to the logic block. The ninth transistor control electrode is coupled to the clock signal CLKA. The ninth transistor second flow electrode is coupled to the second supply voltage.
As discussed in more detail below, the modified full-rail differential logic circuits of the invention are capable of efficient use under heavy loads and are therefore more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.